1. Field of the Invention
The present invention relates to digital level shifters and more particularly to CMOS level shifters.
2. Description of the Prior Art
Level shifters typically provide an output signal shifted in voltage level from an input signal voltage level. A wide variety of digital electronic devices employ level shifters to shift the voltage levels at which logic functions are conducted by various circuits within the device. Due to a number of economic and design considerations some circuits such as, for example, timing circuits may employ relatively low voltage levels to represent logical LOW or HIGH signal values while other circuits such as, for example, erasable programmable read-only memories (EPROMs) may require generally higher voltage levels (for example, to inject electrons into a floating gate in order to program the EPROM). Level shifters can provide a suitable interface between circuits operating a different voltage levels thereby obviating the need to design all of the circuits to operate at the same voltage levels. A savings in the total amount of power dissipated by a digital electronic device can be obtained by operating some of the circuits at lower voltage levels.
Level shifters can be configured in a number of different circuits and incorporate several different transistor design technologies. Typically, level shifters incorporating CMOS transistor designs provide a greater savings in power consumption over circuit designs incorporating p-channel transistors, n-channel transistors, or bipolar transistors alone. CMOS level shifters, however, suffer from a relatively slow output signal transition speed which generally limits their operating frequency to the kilohertz region.
One type of prior art CMOS level shifter incorporates two pairs of complementary metal oxide semiconductor transistors with each pair having a first and second transistor of opposite conductivity type connected together and respectively connected to a first and second voltage source. The gates of the p-channel transistors in each pair are bridged by a signal inverter and the gates of the n-channel transistors in each pair are cross connected to the transistor interconnection of the opposing transistor pair. An input signal is provided to the gate of the first pair p-channel transistor and an inverted or non-inverted output signal may be derived from the transistor interconnections of the first and second transistor pairs respectively.
In an initial state, the p-channel transistor of one pair and the n-channel transistor of the opposing pair are in a conducting or "of" state, and the opposite p-channel and n-channel transistors in a non-conducting or "off" state. When the input signal voltage level shifts, the first two transistors will turn off and the other p-channel transistor and opposing transistor pair n-channel transistor will turn on. During the transition, however, the p-channel transistors will switch conducting states more quickly than the n-channel transistors, resulting in the final conducting state p-channel transistor pulling up against the drain of its paired n-channel transistor until the voltage level between the two transistors changes sufficiently to turn on the opposing pair n-channel transistor. This complementary transistor pair transition phase draining characteristic places a severe restriction on the size ratios of the complementary tansistors in each pair and also restricts the operating frequency of the level shifter. Transition phase draining also increases the transient power consumption of the CMOS level shifter.
Thus there exists a need for a faster CMOS level shifter in which transistor pair transition phase draining is minimized.